1. Technical Field
The invention relates to a method of manufacturing a semiconductor device, and relates to, for example, a technique applicable to a method of manufacturing a semiconductor device including an etching process using a hard mask.
2. Related Art
In methods of manufacturing a semiconductor device, an interconnect layer may be formed by, for example, etching using a hard mask. In this manner, techniques including a process of forming an interconnect layer by etching using a hard mask include, for example, techniques disclosed in Japanese Unexamined Patent Publication No. 2003-100871, Pamphlet of International Publication No. WO2007/043634, and Japanese Unexamined Patent Publication No. 2002-43419.
Japanese Unexamined Patent Publication No. 2003-100871 relates to an interconnect formation method using a double hard mask in which a first hard mask layer and a second hard mask layer are laminated in order. This technique discloses that the second hard mask includes a material selected from a group consisting of aluminized titanium, aluminum titanium nitride, titanium nitride, aluminum nitride, aluminized tantalum and aluminum tantalum nitride.
Pamphlet of International Publication No. WO2007/043634 relates to a method of manufacturing a multilayer interconnect in which a first insulating film for a mask, a metal or metal compound, and a second insulating film for a mask are formed in order on an insulating film to be etched. Japanese Unexamined Patent Publication No. 2002-43419 relates to a method of manufacturing a semiconductor device using a multilayer hard mask layer constituted by a first insulating hard mask layer, a second insulating hard mask layer, and a third insulating hard mask layer.
In the formation of an interconnect layer having a dual damascene structure, an insulating interlayer constituted by a low dielectric constant film may be etched using a hard mask. However, the exposure of the low dielectric constant film when a photoresist at the time of patterning the hard mask is removed by an ashing process may cause a concern of the low dielectric constant film being damaged. In this case, a problem such as an increase in the dielectric constant of the low dielectric constant film occurs.
In order to suppress this, a method of using a hard mask constituted by a multilayer mask film has been examined. However, in such a hard mask, it has been difficult to sufficiently secure etching selectivity between mask films adjacent to each other. In this case, when a trench pattern or a via pattern is formed, there is a concern that defective patterning may occur. In this case, a reduction in the reliability of an interconnect being formed is caused.
For this reason, a method of manufacturing a semiconductor device which is capable of realizing high interconnect reliability while suppressing damage due to an ashing process has been required.
Other problems and novel features will be made clearer from the description and the accompanying drawings of the present specification.